Many electrical and computer applications and components have critical timing requirements that compel generation of periodic clock waveforms that are precisely synchronized with a reference clock waveform. A phase-locked loop ("PLL") is one type of circuit that is widely used to provide an output signal having a precisely controlled frequency that is synchronous with the frequency of a received or input signal. Wireless communication devices, frequency synthesizers, multipliers and dividers, single and multiple clock generators, and clock recovery circuits are but a few examples of the manifold implementations of PLLs.
Frequency synthesis is a particularly common technique used to generate a high frequency clock from a lower frequency reference clock. In microprocessors, for example, an on-chip PLL can multiply the frequency of a low frequency reference (off-chip) clock, typically in the range of 1 to 4 MHz, to generate a high frequency output clock, typically in the range of 10 to over 200 MHz, that is precisely synchronized with the lower frequency reference clock. Another common use of PLLs is recovery of digital data from serial data streams by locking a local clock signal onto the phase and frequency of the data transitions. The local clock signal is then used to clock a flip-flop or latch receiving input from the serial data stream.
FIG. 1 is a block diagram of a typical PLL 10. PLL 10 comprises phase/frequency detector 12, charge pump 14, loop filter 16, oscillator 18 and frequency divider 20. PLL 10 receives a reference clock signal CLK.sub.REF having a frequency F.sub.REF and generates an output clock signal CLK.sub.OUT having a frequency F.sub.OUT that is synchronized with the reference clock signal in phase. The output clock frequency may be an integer (N) multiple of the reference frequency; with the parameter N set by frequency divider 20. Hence, for each reference signal period, there are N output signal periods or cycles.
Phase detector 12 receives on its input terminals two clock signals CLK.sub.REF and CLK.sub.OUT * (CLK.sub.OUT, with its frequency F.sub.OUT divided down by frequency divider 20). In a conventional arrangement, detector 12 is a rising edge detector that compares the rising edges of the two clock signals. Based on this comparison, detector 12 generates one of three states. If the phases of the two signals are aligned, the loop is "locked". Neither the UP nor the DOWN signal is asserted and oscillator 18 continues to oscillate at the same frequency. If CLK.sub.REF leads CLK.sub.OUT *, than oscillator 18 is oscillating too slowly and detector 12 outputs an UP signal proportional to the phase difference between CLK.sub.REF and CLK.sub.OUT *. Conversely, if CLK.sub.REF lags CLK.sub.OUT *, than oscillator 18 is oscillating too quickly and detector 12 outputs a DOWN signal proportional to the phase difference between CLK.sub.REF and CLK.sub.OUT *. The UP and DOWN signals typically take the form of pulses having a width or duration corresponding to the timing difference between the rising edges of the reference and output clock signals. They have a complementary relationship such that neither is asserted at the same time and, if one is asserted, the other is not asserted.
Charge pump 14 generates a current I.sub.CP that controls the oscillation frequency F.sub.OUT of oscillator 18. I.sub.CP is dependent on the signal output by phase detector 12. If charge pump 14 receives an UP signal from detector 12, indicating that CLK.sub.REF leads CLK.sub.OUT *, I.sub.CP is increased. If charge pump 14 receives a DOWN signal from detector 12, indicating that CLK.sub.REF lags CLK.sub.OUT *, I.sub.CP is decreased. If neither an UP nor a DOWN signal is received, indicating that the clock signals are aligned, charge pump 14 does not adjust I.sub.CP.
Loop filter 16 is positioned between charge pump 14 and oscillator 18. Application of the charge pump output current I.sub.CP to loop filter 16 develops a voltage V.sub.LF at the output of filter 16. Filter 16 also removes out-of-band, interfering signals. V.sub.LF is then applied to oscillator 18 to control the frequency F.sub.OUT of the output clock signal. A common configuration for a loop filter in a PLL is a simple single-pole, low-pass filter that can be realized with a single resistor and capacitor.
Oscillator 18 generates an oscillating output signal CLK.sub.OUT having a frequency F.sub.OUT proportional to the voltage V.sub.LF applied to oscillator 18. Conventional oscillators typically oscillate about a specific center frequency and have a relatively narrow frequency range or bandwidth. When CLK.sub.REF leads CLK.sub.OUT *, charge pump 14 increases I.sub.CP to develop a greater V.sub.LF at the output of loop filter 16 which, in turn, causes oscillator 18 to increase F.sub.OUT. Conversely, when CLK.sub.REF lags CLK.sub.OUT *, charge pump 14 decreases I.sub.CP to develop a lesser V.sub.LF at the output of loop filter 16 which, in turn, causes oscillator 18 to decrease F.sub.OUT. When CLK.sub.REF and CLK.sub.OUT * are aligned, V.sub.LF is not adjusted, and F.sub.OUT is kept constant. In this state, PLL 10 is in a "locked" condition.
The output clock signal is also looped back through (in some applications) frequency divider 20. The resultant output CLK.sub.OUT * is provided to phase/frequency detector 12 to facilitate the phase-locked loop operation. Frequency divider 20 divides F.sub.OUT by the multiplication factor N to obtain a divided clock. Divider 20 may be implemented using counters, shift registers, or through other methods familiar to those of skill in the art. Thus, PLL 10 compares the reference clock phase to the divided clock phase and eliminates any detected phase difference between the two by adjusting the frequency of the output clock.
In many applications, it is desirable and advantageous to integrate all of the components of a phase-locked loop on a semiconductor chip. On-chip phase-locked loops are often implemented using CMOS technology. Due to the high temperature coefficients displayed by some of the integrated components, however, it is difficult to maintain a constant loop bandwidth over temperature variations. This is especially problematic in digital CMOS, which requires the use of integrated circuitry components having particularly high temperature coefficients, such as well resistors.
In view of the above, there is a need for a phase-locked loop that demonstrates a stable bandwidth in relation to temperature variations.